1. Field of the Invention
The present invention generally relates to the formation of integrated circuits, and, more particularly, to a process flow for forming a contact layer including bumps, wherein the contact layer is configured to provide copper-based contact areas connected to a lower-lying metallization layer for directly attaching an appropriately formed package or carrier substrate to a die carrying one or more integrated circuits.
2. Description of the Related Art
In manufacturing integrated circuits, it is usually necessary to package a chip and provide leads and terminals for connecting the chip circuitry with the periphery. In some packaging techniques, chips, chip packages or other appropriate units may be connected by means of solder balls, formed from so-called solder bumps, that are formed on a corresponding layer, which will be referred to herein as a contact layer, of at least one of the units, for instance on a dielectric passivation layer of the microelectronic chip. In order to connect the microelectronic chip with the corresponding carrier, the surfaces of two respective units to be connected, i.e., the microelectronic chip comprising, for instance, a plurality of integrated circuits, and a corresponding package, have formed thereon adequate pad arrangements to electrically connect the two units after reflowing the solder bumps provided at least on one of the units, for instance on the microelectronic chip. In other techniques, solder bumps may have to be formed that are to be connected to corresponding wires, or the solder bumps may be brought into contact with corresponding pad areas of another substrate acting as a heat sink. Consequently, it may be necessary to form a large number of solder bumps that may be distributed over the entire chip area, thereby providing, for example, the I/O capability as well as the desired low-capacitance arrangement required for high frequency applications of modern microelectronic chips that usually include complex circuitry, such as microprocessors, storage circuits and the like, and/or include a plurality of integrated circuits forming a complete complex circuit system.
In modern integrated circuits, highly conductive metals such as copper and alloys thereof, are used to accommodate the high current densities encountered during the operation of the devices. Consequently, the metallization layers may comprise metal lines and vias formed from copper or copper alloys, wherein the last metallization layer may provide contact areas for connecting to the solder bumps to be formed above the copper-based contact areas. The processing of copper in the subsequent process flow for forming the solder bumps, which is itself a highly complex manufacturing phase, may be performed on the basis of the well-established metal aluminum that has effectively been used for forming solder bump structures in complex aluminum-based microprocessors. For this purpose, an appropriate barrier and adhesion layer is formed on the copper-based contact area, followed by an aluminum layer. Subsequently, the contact layer including the solder bumps is formed on the basis of the aluminum-covered contact area.
In order to provide hundreds or thousands of mechanically well-fastened solder bumps on corresponding pads, the attachment procedure of the solder bumps requires a careful design since the entire device may be rendered useless upon failure of only one of the solder bumps. For this reason, one or more carefully chosen layers are generally placed between the solder bumps and the underlying substrate or wafer including the aluminum-covered contact areas. In addition to the important role these interfacial layers, herein also referred to as underbump metallization layers, may play in endowing a sufficient mechanical adhesion of the solder bump to the underlying contact area and the surrounding passivation material, the underbump metallization has to meet further requirements with respect to diffusion characteristics and current conductivity. Regarding the former issue, the underbump metallization layer has to provide an adequate diffusion barrier to prevent the solder material, frequently a mixture of lead (Pb) and tin (Sn), from attacking the chip's underlying metallization layers and thereby destroying or negatively affecting their functionality. Moreover, migration of solder material, such as lead, to other sensitive device areas, for instance into the dielectric, where a radioactive decay in lead may also significantly affect the device performance, has to be effectively suppressed by the underbump metallization. Regarding current conductivity, the underbump metallization, which serves as an interconnect between the solder bump and the underlying metallization layer of the chip, has to exhibit a thickness and a specific resistance that does not inappropriately increase the overall resistance of the metallization pad/solder bump system. In addition, the underbump metallization will serve as a current distribution layer during electroplating of the solder bump material. Electroplating is presently the preferred deposition technique, since physical vapor deposition of solder bump material, which is also used in the art, requires a complex mask technology in order to avoid any misalignments due to thermal expansion of the mask while it is contacted by the hot metal vapors. Moreover, it is extremely difficult to remove the metal mask after completion of the deposition process without damaging the solder pads, particularly when large wafers are processed or the pitch between adjacent solder pads decreases.
Although a mask is also used in the electroplating deposition method, this technique differs from the evaporation method in that the mask is created using photolithography to thereby avoid the above-identified problems caused by physical vapor deposition techniques. After the formation of the solder bumps, the underbump metallization has to be patterned to electrically insulate the individual solder bumps from each other.
With reference to FIGS. 1a-1c, a typical conventional process flow will now be described to explain difficulties involved in forming solder bumps of copper-based semiconductor devices in more detail.
FIG. 1a schematically shows a cross-sectional view of a conventional semiconductor device 100 in an advanced manufacturing stage. The semiconductor device 100 comprises a substrate 101, which may have formed therein circuit elements and other microstructural features that are, for convenience, not shown in FIG. 1a. Moreover, the device 100 comprises one or more metallization layers including copper-based metal lines and vias, wherein, for convenience, the last metallization layer 107 is shown, which may comprise a dielectric material and formed therein a metal region 102 that is substantially comprised of copper or a copper alloy. The metallization layer 107 is covered by a corresponding passivation layer 103, except for at least a certain portion of the metal region 102. The passivation layer 103 may be comprised of any suitable dielectric material, such as silicon dioxide and the like. Formed above the copper-based metal region 102 is a barrier/adhesion layer 104, which may be comprised of tantalum, tantalum nitride, titanium, titanium nitride, tantalum nitride or compositions thereof, and the like, wherein the barrier/adhesion layer 104 provides the required diffusion blocking characteristics as well as the corresponding adhesion between an overlying aluminum layer 105 and the copper-based metal region 102. The aluminum layer 105 in combination with the adhesion/barrier layer 104 may be referred to as a terminal metal. The aluminum layer 105 thus defines in combination with the patterned passivation layer 103, the barrier/adhesion layer 104 and the underlying copper-based metal region 102, a contact region 105a, above which a solder bump is to be formed. Moreover, a corresponding resist mask 106 is formed on the device 100 to protect the contact region 105a while exposing the residue of the layer 105 to an etch ambient 108 that typically includes chlorine-based chemicals for efficiently removing aluminum.
The semiconductor device 100 as shown in FIG. 1a may be formed by the following processes. First, the substrate 101 and any circuit elements contained therein may be manufactured on the basis of well-established process techniques, wherein, in sophisticated applications, circuit elements having critical dimensions as small as approximately 50 nm and even less may be formed, followed by the formation of the one or more metallization layers 107 including copper-based metal lines and vias, wherein typically low-k dielectric materials are used for embedding at least the metal lines. Next, the passivation layer 103 may be formed on the last metallization layer 107 by any appropriate deposition technique, such as plasma enhanced chemical vapor deposition (PECVD) and the like. Thereafter, a standard photolithography process is performed to form a photoresist mask (not shown) having a shape and dimension that substantially determines the shape and dimension of the contact region 105a and thus substantially determines, in combination with the material characteristics of the layers 105 and 104, the drive current capability of the finally obtained electrical connection between the metallization layer 107, i.e., the copper-based metal region 102, and a solder bump to be formed above the contact region 105a. Subsequently, the passivation layer 103 may be opened on the basis of the resist mask, which may then be removed by well-established resist removal processes that may include appropriate cleaning steps, as required.
Thereafter, the barrier/adhesion layer 104 may be deposited, for instance, by sputter deposition using well-established process recipes for tantalum, tantalum nitride, titanium, titanium nitride, or other similar metals and compounds thereof as are typically used in combination with copper metallizations to effectively reduce copper diffusion and enhance adhesion of the overlying aluminum layer 105. Next, the aluminum layer may be deposited, for instance by sputter deposition, chemical vapor deposition and the like, followed by a standard photolithography process for forming the resist mask 106.
Next, the reactive etch ambient 108 is established, which may require a complex chlorine-based etch chemistry, wherein the process parameters may require an accurate process control to substantially prevent undue yield loss. The etch process 108 may also comprise a separate etch step for etching through the barrier/adhesion layer 104 and may also include a wet strip process for removing any corrosive etch residues generated during the complex aluminum etch step.
FIG. 1b schematically shows the semiconductor device 100 in a further advanced manufacturing stage, in which a further passivation layer 109, which is also referred to as a last passivation layer, is formed above the contact region 105a, followed by a resist mask 110, which is configured to act as an etch mask in a subsequent etch process for opening the last passivation layer 109. The layer 109 may be formed on the basis of well-established spin-on techniques or other deposition methods, while the resist mask 110 may be formed on the basis of established photolithography techniques. Based on the resist mask 110, the passivation layer 109, typically comprised of polyimide, may be etched to expose at least a portion of the contact region 105a. 
According to alternative approaches, the aluminum layer 105 and the barrier/adhesion layer 104 may be deposited on the metallization layer 107 prior to the formation of the passivation layer 103. Thereafter, the passivation layer 103 may be patterned, followed by the highly complex aluminum etch process 108, including any etch and cleaning processes for also patterning the barrier/adhesion layer 104. Thereafter, the last passivation layer 109 may be deposited and further processing may be continued, as is also described above with reference to FIG. 1b. 
FIG. 1c schematically shows the semiconductor device 100 in a further advanced manufacturing stage. Here, the device 100 comprises an underbump metallization layer 111, which is shown in this example as comprising at least a first underbump metallization layer 111a and a second layer 111b, which are formed on the patterned last passivation layer 109 and on the contact region 105a. The underbump metallization layer 111 may be comprised of any appropriate layer combination so as to provide the required electrical, thermal and mechanical characteristics, as well as reducing or avoiding a diffusion of material of an overlying solder bump 112 into lower-lying device regions. Moreover, a resist mask 113 is formed which comprises an opening that substantially defines the shape and lateral dimensions of the solder bump 112.
Typically, the device 100 as shown in FIG. 1c may be formed by the following processes. First, the underbump metallization layer 111, for instance the layer 111b, may be formed by sputter deposition for forming a titanium tungsten layer (TiW), since this material composition is frequently used in view of its well-approved diffusion blocking and adhesion characteristics. Thereafter, further sub-layers of the underbump metallization layer 111 may be formed, such as the layer 111a, which may be provided in the form of a chromium/copper layer, which may be followed by a further substantially pure copper layer. The layer(s) 111a may be formed by sputter deposition in accordance with well-established recipes. Next, a further photolithography process is performed in order to form the resist mask 113, thereby providing a deposition mask for the subsequent electroplating process for the deposition of the solder bump 112. Thereafter, the resist mask 113 may be removed and the underbump metallization layer 111 may be patterned while using the solder bump 112 as an etch mask, thereby providing electrically insulated solder bumps 112. Depending on process requirements, the solder bumps 112 may be reflowed to create rounded solder balls (not shown) which may then be used for contacting an appropriate carrier substrate.
As is evident from the process flow described with reference to FIGS. 1a-1c, a highly complex process flow is required for providing the contact region 105a to enable the formation of the bump structure including the solder bump 112 and the underlying underbump metallization layer 111. However, even though the highly conductive copper is used for the metal region 102, the finally achieved current drive capability of the bump structure is significantly affected by the characteristics of the contact region 105a, i.e., by the aluminum layer 105 and the barrier/adhesion layer 104. Consequently, in the conventional procedure, a highly complex process flow, including the complex aluminum etch sequence, is involved while only resulting in a moderate electrical performance of the resulting bump structure. This situation may even become worse as aluminum pitting and also delamination of the polyimide layer 109 may occur, which may especially be caused by open copper areas, i.e., by areas similar to the region 102, that are referred to as open areas, typically provided at the die region to act as a die border, or in scribe lanes of the wafer when these scribe lanes are provided on the front side. In these open areas, the passivation layer 109 may not be provided, thereby promoting a delamination of the polyimide layer 109 at any interfaces between open areas and regular die regions. Thus, aluminum pitting and/or polyimide delamination may significantly contribute to yield loss in the above-described manufacturing sequence.
In view of the situation described above, a need exists for an improved technique that enables formation of a bump structure connected to copper-based metal regions, while avoiding one or more of the problems identified above or at least reducing the effects thereof.